Lab 8: Convolution TIMS Week 1

Lab 8: Convolution TIMS Week 1 

 

Introduction 

The following lab deals with convolution in TIMS. In signals and systems, convolution is a mathematical operation that describes how one signal modifies or filters another. It represents the combined effect of two overlapping signals. By "convolving" a signal with a system's impulse response, you can determine the system's output for that signal. Essentially, convolution provides a way to understand the behavior of linear, time-invariant systems. This foundational operation underpins much of modern technology, from audio processing to telecommunications.   

Procedure 

Part A – Setting up the PC-MODULES CONTROLLER and software 

1. Insert the PC-MODULES CONTROLLER board into the TIMS device. 

2. Link the PC-MODULES CONTROLLER module to the computer using the provided USB cable. Ensure the module is recognized, typically signaled by a short sound from the computer. 

3. Open the TIMS S&S SFP application on your computer. 

 

Note: When concluding the experiment, it's advised to use the STOP button on the SFP instead of the STOP button in the LabVIEW window's top. Doing so ensures a systematic shutdown and closure of the active USB communication channels. 

 

Experiment 

Part 1 – Setting up 

1. Set up the model with the following configurations: 

   - Choose a SAMPLE CLK rate close to 1kHz on the DIGITAL UTILITIES Module. 

   - For the SEQUENCE GENERATOR, set DIPS to UP/UP for a short sequence. 

   - Referring to Figure 2, ensure the gains a1 and a2 remain disconnected. 

2. The necessary signal emerges from the SEQUENCE GENERATOR SYNC output as a 5V signal. To reduce its amplitude, utilize the a0 GAIN function in the SFP V2 software. Examine the signal with a scope to confirm a repetitive single 1V pulse within a 32-pulse frame. The pulse should last around 1ms. To achieve an exact 1V pulse amplitude, modify the a0 gain. Consider: if gain acts as a multiplier, what factor multiplies 5V to produce 1V? This factor will be your gain value (hint: it's less than 1). Adjust the SCOPE's trigger for a consistent display. 

  

Figure 1: 1 pulse every 32 periods from following instructions. 

 

1 pulse is observed every 32 periods as the signal is based on 1kHz. The emitted pulse serves as the clock for the unit delay. Due to this and the application of 1kHz to the clock, only one pulse appears every 32 seconds. 

 

Figure 2: corrected waveforms and signals for experiment, with correct outputs and inputs. 

 

I used .28 for a0. 

 

Note: The incoming pulse is synchronized with the same clock as the delay units. Therefore, it's inherently a discrete signal and can be directly fed into the unit delay without the S/H block. 

 

Part 2 – unit pulse response 

Before analyzing the system's response, ensure you set the delay line "tap" gains. For this initial test, set b0 to 0.3, b1 to 0.5, and b2 to -0.2 (refer to Figure 1). These values have been picked for their variety and relevance to this task. Adjust each gain using the SFP and verify your configurations with the scope. 

  

Question 1: 

- Show the input signal of the delay line (specifically at the first z-1 block input) alongside the ADDER's output signal. Determine and document the amplitude of every pulse in the output sequence, labeling them as h[0], h[1], and h[2]. 

 

Figure 3: input delay lines 

 

The following figure is the graph that should be displayed from replicating the experiment. 

 

Table 1: Recorded and comparison of the amplitude of each pulse in the output sequence 

 

Observe that the system's output consists of three consecutive pulses, their amplitudes reflecting the ratios of the adder's input gains. Is this pattern anticipated from Figure 1? Certainly, as the single input pulse creates scaled and delayed replicas while moving through the delay line, which are subsequently summed in the adder. This provides us the system's reaction to a standalone pulse. We can hence characterize the unit pulse response h(n) as the outcome when the input pulse's amplitude is one. From your findings, validate that for the unit pulse h(0) = b0, h(1) = b1, and h(2) = b2 in this scenario. It's typical in real-world systems, be they electrical or mechanical, to detect delayed energy. This can be attributed to mechanical inertia or energy retention in electrical circuit components like capacitors and inductors. 

 

Part 3 – The superposition sum 

3. Modify the SEQUENCE GENERATOR CLK RATE to half its original setting, which will double the SYNC pulse width, simulating two consecutive pulses. Choose the 500Hz output option from the DIGITAL UTILITIES. 

 

NOTE: The version of DIGITAL UTILITIES you possess, such as V1 (unmarked), might require an inversion of the 1kHz clock signal to ensure the slower 500Hz clock aligns with the positive edge of the 1kHz clock, maintaining consistent clock polarity. If using V2 (marked), confirm that the DIP switches are set to the '+' polarity for the CLK edge. 

With the gain configurations from Part 2, inspect the output signal. Observe that it features four non-zero pulses in each frame. Document the amplitude of each pulse. 

 

4. Confirm that the resulting sequence is essentially the combination of two staggered unit pulse responses. 

 

Figure 4: Adjusted SEQUENCE GENERATOR CLK RATE to be halved 

 

 

Figure 5: unit pulse pair summation graph 

 

The shifted and superimposed graphs from part 2 equal that of part 3 because adding waveforms can be seen to be the same as adjusting a waveform to be halved as displayed in figure 4. Using the original 1kHz signal and halving it with the Digital Utilities module produces a 500Hz signal. This doubles the pulse width, simulating two adjacent signals. 

Table 2: updated values for h(x) and b(x). 

 

Note: For a linear system where y1 + y2 equals the sum of S(x1 + x2), it's possible to evaluate the system using multiple combined pulses, leading to superposition. If this activity were to include two or more continuous pulses, the anticipated output would be the aggregate of impulse responses corresponding to successive impulse inputs. 

 

Part 4: rectified sinewave at input 

In this section, the input is more intricate than in Part 3, consisting of a sequence of three or four pulses with varying amplitudes. The origin of this signal is the ARB 1 output, post-rectification. This analog signal then progresses to the SAMPLE/HOLD block for sampling, resulting in our discrete pulse sequence. It's important to highlight that while the SAMPLE & HOLD derives its clock signal from ARB 2, both share an internal clock, ensuring consistency in the scope displays. 

  

Even though the signal undergoes sampling and becomes "discrete," it doesn't transition to a "digital" state. This differentiation is crucial. The signal now represents a series of discrete samples from its original form. Further discussions about sampling and its ramifications will be addressed in subsequent experiments. 

  

Configuration details: 

- ARB1: Set to a 100 Hz sinewave with a peak of 2V. 

- ARB2: Digital CLK with a frequency of 800Hz. 

  

Before proceeding, ensure the sinewave from ARB1 displays a 100Hz frequency and a 2V peak prior to the RECTIFIER stage. For this exercise, consider the sinewave as a continuous signal, disregarding any minute steps, as they don't impact our process. 

Figure 6: sinewave rectified input 

-.5 to 2.3V is the peak to peak values of the ARB1 sinewave as pictured above. 

 

Question 2 

The half-wave rectifier outputs half the amplitude of the sine wave because it allows only one half of the input wave (in this case, the sine wave) to pass through, while blocking the other half. 

 

5. Retaining the b gain values from Part 1 (specifically, b0 = 0.3, b1 = 0.5, and b2 = -0.2), showcase both the input (that is, the output from the SAMPLE-HOLD as illustrated in Figure 5a) and output signals. Examine the input and output of the S&H to understand its role. Validate that there are 8 samples for each half-wave of the sine input, which aligns with expectations given the 800 Hz sampling clock and the 100 Hz input sinewave. 

Figure 7: Both graphs of half-rectified sinusoid and discrete output from SAMLE/HOLD 

 

The S/H (Sample and Hold) block captures the input when it detects a trigger event at the trigger port. 

 

  

Conclusion  

Convolution is a fundamental mathematical operation in signals and systems that provides a framework for understanding how systems respond to various inputs. It describes the manner in which an input signal is processed or transformed by a system, capturing the integral relationship between the system's inherent characteristics (often represented by its impulse response) and any given input. In a lab setting, convolution becomes especially critical. By applying known signals to a system and observing the outputs, students and researchers can deduce the system's behavior, validate theoretical models, and troubleshoot anomalies. Furthermore, the hands-on experience with convolution in labs enhances comprehension, bridging the gap between abstract mathematical concepts and tangible real-world applications.